MTP60N05HDL - TMOS POWER FET
MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MTP60N05HDL/D Product Preview HDTMOS E-FET.™ Power Field Effect Transistor N Channel Enhancement Mode Silicon Gate This advanced high cell density HDTMOS power FET is designed to withstand high energy in the avalanche and commutation modes.
The new energy efficient design also offers a drain to source diode with a fast recovery time.
Designed for low voltage, high speed switching applications
MTP60N05HDL Features
* S) VGS, GATE
* TO
* SOURCE VOLTAGE (VOLTS) 8.0 VGS 6.0 QT 40 4.0 Q1 2.0 Q3 VDS 0 10 20 30 40 50 QG, TOTAL GATE CHARGE (nC) Q2 TJ = 60°C ID = 5.0 A 20 10 0 0 30 60 50 1000 VDD = 25 V ID = 60 A VGS = 5.0 V TJ = 25°C t, TIME (ns) tr tf td(off) 100 td(on) 10 1.0 10 RG, GATE RESISTANCE (
