MTP75N03HDL - TMOS POWER FET
MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MTP75N03HDL/D Advanced Information HDTMOS E-FET ™ High Density Power FET N Channel Enhancement Mode Silicon Gate This advanced high cell density HDTMOS E FET is designed to withstand high energy in the avalanche and commutation modes.
This new energy efficient design also offers a drain to source diode with a fast recovery time.
Designed for low voltage, high speed swi
MTP75N03HDL Features
* VGS 16 12 8 4 0 70 20 28 24 10000 TJ = 25°C ID = 75 A VDD = 15 V VGS = 5 V VDS , DRAIN
* TO
* SOURCE VOLTAGE (VOLTS) t, TIME (ns) 1000 tr 100 tf td(off) td(on) 10 1 10 RG, GATE RESISTANCE (OHMS) 100 www.DataSheet4U.com Figure 8. Gate
* To
* Source and Drain
* To
