S7L1618U2M Datasheet - NETSOL

S7L1618U2M 512Kx36 & 1Mx18 DDRII+ CIO BL2 SRAM w/ ODT

The S7L1636U2M and S7L1618U2M are 18,874,368-bits DDR Common I/O Synchronous Pipelined Burst SRAMs. They are organized as 524,288 words by 36bits for S7L1636U2M and 1,048,576 words by 18 bits for S7L1618U2M. Address, data inputs, and all control signals are synchronized to the input clock (K or K). .

SSSS7777LLLL1111666613318668UUUU2222MMMM 551122KKxx3366&&11MMxx1188DDDDRRIII+I+CCIOIOBBLL22SSRRAAMMww//OODDTT 18Mb DDRII+ CIO BL2 w/ ODT SRAM Specification (2.5 Clock Read Latency) 165FBGA with Pb & Pb Free (ROHS Compliant) NETSOL RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This.

S7L1618U2M Features

* Key Parameters

* 1.8V+0.1V/-0.1V Power Supply.

* DLL circuitry for wide output data valid window and future fre- quency scaling.

* I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/ Part Number Org. Freq. (MHz) Cycle Access Time Time RoHS (ns) (ns) -0.1V for 1

S7L1618U2M Datasheet (365.34 KB)