The S7L3236U2M and S7L3218U2M are 37,748,736-bits DDR Common I/O Synchronous Pipelined Burst SRAMs.
They are organized as 1,048,576 words by 36bits for S7L3236U2M and 2,097,152 words by 18 bits for S7L3218U2M.
Address, data inputs, and all control signals are synchronized to the input clock (K or K)
SS77LL33223366UU22MM SS77LL33221188UU22MM 11MMxx3366 && 22MMxx1188 DDDDRRIIII++ CCIIOO BBLL22 SSRRAAMM ww// OODDTT 36Mb DDRII+ CIO BL2 w/ ODT SRAM Specification (2.5 Clock Read Latency) 165FBGA with Pb & Pb Free (ROHS Compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO NETSOL PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
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S7L3218U2M Features
* Key Parameters
* 1.8V+0.1V/-0.1V Power Supply.
* DLL circuitry for wide output data valid window and future fre- quency scaling.
* I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/-0.1V for 1.8V I/O.
* Pipelined, double-data rate operation.
* Commo
Datasheet Details
S7L3218U2M, S7L3236U2M
NETSOL
352.89 KB
1mx36 & 2mx18 ddrii+ cio bl2 sram w/ odt.
This datasheet PDF includes multiple part numbers: S7L3218U2M, S7L3236U2M.
Please refer to the document for exact specifications by model.
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