74LVC3G06 Datasheet PDF - NXP Semiconductors Triple inverter Specs

74LVC3G06 - Triple inverter

Datasheet Summary

Description

The 74LVC3G06 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families.

Inputs can be driven from either 3.3 V or 5 V devices.

This feature allows the use of this device in a mixed 3.3 V and 5 V environment.

Features

s s s s Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant input/output for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: x JESD8-7 (1.65 V to 1.95 V) x JESD8-5 (2.3 V to 2.7 V) x JESD8-B/JESD36 (2.7 V to 3.6 V). ESD protection: x HBM EIA/JESD22-A114-B exceeds 2000 V x MM EIA/JESD22-A115-A exceeds 200 V.
24 mA output drive (VCC = 3.0 V) CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept vo.

Datasheet Details

Part number	74LVC3G06
Manufacturer	NXP Semiconductors
File Size	110.58 KB
Description	Triple inverter
Datasheet	74LVC3G06 Datasheet
Additional preview pages of the 74LVC3G06 datasheet.

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Full PDF Text Transcription

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74LVC3G06 Triple inverter with open-drain output Rev. 03 — 01 February 2005 www.DataSheet4U.com Product data sheet 1. General description The 74LVC3G06 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall time. This device is fully speciﬁed for partial power-down applications using Ioff. The Ioff circuitry disables the output, preventing the damaging backﬂow current through the device when it is powered down. The 74LVC3G06 provides three inverting buffers.

Published: Mar 27, 2010 |