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74LVC3G06 Triple inverter

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Description

74LVC3G06 Triple inverter with open-drain output Rev.03 * 01 February 2005 www.DataSheet4U.com Product data sheet 1.General .
The 74LVC3G06 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families.

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Features

* s s s s Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant input/output for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: x JESD8-7 (1.65 V to 1.95 V) x JESD8-5 (2.3 V to 2.7 V) x JESD8-B/JESD36 (2.7 V to 3.6 V). ESD protection: x HBM EIA/JESD22-A114-B exceeds

Applications

* using Ioff. The Ioff circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74LVC3G06 provides three inverting buffers. The output of this device is an open drain and can be connected to other open-drain outputs to implement active-LOW

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