74LVC3G17 Datasheet - NXP

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74LVC3G17 Triple non-inverting Schmitt trigger

74LVC3G17 Triple non-inverting Schmitt trigger with 5 V tolerant input Rev.03 * 31 January 2005 Product data sheet 1.General .
The 74LVC3G17 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families.

74LVC3G17_PhilipsSemiconductors.pdf

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Datasheet Details

Part number:

74LVC3G17

Manufacturer:

NXP ↗

File Size:

91.41 KB

Description:

Triple non-inverting Schmitt trigger

Features

* s s s s Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant input/output for interfacing with 5 V logic High noise immunity ESD protection: x HBM EIA/JESD22-A114-B exceeds 2000 V x MM EIA/JESD22-A115-A exceeds 200 V. ±24 mA output drive (VCC = 3.0 V) CMOS low power consumption Latch-up perfo

Applications

* using Ioff. The Ioff circuitry disables the output, preventing the damaging backﬂow current through the device when it is powered down. The 74LVC3G17 provides three non-inverting buffers with Schmitt-trigger action. It is capable of transforming slowly changing input signals into sharply deﬁned, jit

74LVC3G17 Distributors

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74LVC3G17 Triple non-inverting Schmitt trigger NXP

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