BLD6G21LS-50 Description
BLD6G21L-50; BLD6G21LS-50 TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor Rev.01 * 28 October 2009 Objective data sheet 1..
The BLD6G21L-50 and BLD6G21LS-50 incorporate a fully integrated Doherty solution using NXP’s state of the art GEN6 LDMOS technology.
BLD6G21LS-50 Features
* I Typical TD-SCDMA performance at frequencies from 2010 MHz to 2025 MHz: N Average output power = 8 W N Power gain = 13.5 dB N Efficiency = 42 % I Fully optimized integrated Doherty concept: N integrated asymmetrical power splitter at input N integrated power combiner N peak biasing down to 0 V N low
BLD6G21LS-50 Applications
* at frequencies from 2010 MHz to 2025 MHz. The main and peak device, input splitter and output combiner are integrated in a single package. This package consists of one gate and drain lead and two extra leads of which one is used for biasing the peak amplifier and the other is not connected. It only r
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