GTL2006 Datasheet - NXP

GTL2006 - 13-bit GTL-/GTL/GTL+ to LVTTL translator

The GTL2006 is a 13-bit translator to interface between the 3.3 V LVTTL chip set I/O and the Xeon™ processor GTL */GTL/GTL+ I/O.

The GTL2006 is designed for platform health management in dual processor applications.

SW01091 Figure 1.

Pin configuration PIN DESCRIPTION PIN NUMBER 1 2

GTL2006 Features

* Operates as a GTL

* /GTL/GTL+ to LVTTL sampling receiver or

* 3.0 V to 3.6 V operation

* LVTTL I/O not 5 V tolerant

* Series termination on the LVTTL outputs of 30 Ω

* ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 250

Datasheet Details

GTL2006

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13-bit gtl-/gtl/gtl+ to lvttl translator.

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