* s Bidirectional interface between GTLP and LVTTL logic levels s Variable edge rate control pin to select desired edge rate on GTLP port (VERC) s VREF pin provides external supply reference voltage for receiver threshold adjustibility s Split LVTTL inputs and outputs s Special PVT compensation circui
GTLP10B320 Datasheet (261.02 KB)
GTLP10B320
Fairchild Semiconductor
261.02 KB
10-bit lvttl/gtlp transceiver.
GTLP10B320 10-Bit LVTTL/GTLP Transceiver with Split LVTTL Port and Feedback Path
May 2001 Revised May 2001
GTLP10B320 10-Bit LVTTL/GTLP Transceiver .
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