* s Bidirectional interface between GTLP and LVTTL logic levels s Edge Rate Control to minimize noise on the GTLP port s Power up/down high impedance for live insertion s External VREF pin for receiver threshold s BiCMOS technology for low power dissipation s Bushold data inputs on A Port eliminates t
GTLP18T612 Datasheet (74.88 KB)
GTLP18T612
Fairchild Semiconductor
74.88 KB
18-bit lvttl/gtlp universal bus transceiver.
GTLP18T612 18-Bit LVTTL/GTLP Universal Bus Transceiver
May 1999 Revised September 1999
GTLP18T612 18-Bit LVTTL/GTLP Universal Bus Transceiver
Genera.
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