* s Bidirectional interface between GTLP and TTL logic levels s Edge Rate Control to minimize noise on the GTLP port s Power up/down/off high impedance for live insertion s External VREF pin for receiver threshold s CMOS technology for low power dissipation s 5 V tolerant inputs and outputs on the A-P
GTLP16616 Datasheet (72.89 KB)
GTLP16616
Fairchild Semiconductor
72.89 KB
17-bit ttl/gtlp bus transceiver.
GTLP16616 17-Bit TTL/GTLP Bus Transceiver with Buffered Clock
June 1997 Revised October 1998
GTLP16616 17-Bit TTL/GTLP Bus Transceiver with Buffered.
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