* s Bidirectional interface between GTLP and LVTTL logic levels s Variable Edge Rate Control pin to select desired edge rate on the GTLP backplane (VERC ) s Partitioned as two 8-Bit transceivers with individual latch timing and output control but with a common clock. s Power up/down high impedance for
GTLP16T1655 Datasheet (107.76 KB)
GTLP16T1655
Fairchild Semiconductor
107.76 KB
16-bit lvttl/gtlp universal bus transceiver.
GTLP16T1655 16-Bit LVTTL/GTLP Universal Bus Transceiver
August 1998 Revised April 2000
GTLP16T1655 16-Bit LVTTL/GTLP Universal Bus Transceiver
Gener.
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