* s Bidirectional interface between GTLP and TTL logic levels s Edge Rate Control to minimize noise on the GTLP port s Power up/down/off high impedance for live insertion. s External VREF pin for receiver threshold s CMOS technology for low power dissipation s 5 V tolerant inputs and outputs on the A-
GTLP16617 Datasheet (74.25 KB)
GTLP16617
Fairchild Semiconductor
74.25 KB
17-bit ttl/gtlp synchronous bus transceiver.
GTLP16617 17-Bit TTL/GTLP Synchronous Bus Transceiver with Buffered Clock
June 1997 Revised October 1998
GTLP16617 17-Bit TTL/GTLP Synchronous Bus T.
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