* s Bidirectional interface between GTLP and LVTTL logic levels s Edge Rate Control to minimize noise on the GTLP port s Power up/down high impedance for live insertion s External VREF pin for receiver threshold adjustability s BiCMOS technology for low power dissipation s Bushold data inputs on A Por
GTLP17T616 Datasheet (93.18 KB)
GTLP17T616
Fairchild Semiconductor
93.18 KB
17-bit lvttl/gtlp bus transceiver.
GTLP17T616 17-Bit LVTTL/GTLP Bus Transceiver with Buffered Clock
January 2000 Revised February 2000
GTLP17T616 17-Bit LVTTL/GTLP Bus Transceiver wit.
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