HEF40160B

4-bit synchronous decade counter with asynchronous reset

NXP

HEF40160B General Description

The HEF40160B is a fully synchronous edge-triggered 4-bit decade counter with a clock input (CP), an overriding asynchronous master reset (MR), four parallel data inputs (P0 to P3), three synchronous mode control inputs (parallel enable (PE), count enable parallel (CEP) and count enable trickle (CET.

HEF40160B Datasheet (155.58 KB)

HEF40160B Datasheet Preview — Preview of HEF40160B PDF

Datasheet Details

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HEF40160B

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NXP ↗

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155.58 KB

Description:

4-bit synchronous decade counter with asynchronous reset.
INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download:

* The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HE.

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HEF40160B 4-bit synchronous decade counter with asynchronous reset NXP

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HEF40160B General Description

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