HEF4015B Datasheet (nexperia) - Dual 4-bit static shift register

HEF4015B, Dual 4-bit static shift register

The HEF4015B is a dual edge-triggered 4-bit static shift register (serial-to-parallel converter).

Each shift register has a serial data input (nD), a clock input (nCP), four fully buffered parallel outputs (Q0 to Q3) and an overriding asynchronous master reset input (nMR).

Information present on nD

HEF4015B Features

* Wide supply voltage range from 3.0 V to 15.0 V

* CMOS low power dissipation

* High noise immunity

* Tolerant of slow clock rise and fall times

* Fully static operation

* 5 V, 10 V, and 15 V parametric ratings

* Standardized symmetrical output