NT5CB128M16FP Key Features
- JEDEC DDR3 pliant
- 8n Prefetch Architecture
- Differential Clock(CK/) and Data Strobe(DQS/)
- Double-data rate on DQs, DQS and DM
- Signal Integrity
- Configurable DS for system patibility
- Configurable On-Die Termination
- ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (240 ohm ± 1%)
- Data Integrity
- Auto Self Refresh (ASR) by DRAM built-in TS