NT5CB128M16FP - Industrial and Automotive DDR3(L) 2Gb SDRAM

This page provides the datasheet information for the NT5CB128M16FP, a member of the NT5CB256M8FN Industrial and Automotive DDR3(L) 2Gb SDRAM family.

Datasheet Summary

The 2Gb Double-Data-Rate-3 (DDR3(L)) is double data rate architecture to achieve high-speed operation.

It is internally configured as an eight bank DRAMs.

The 2Gb chip is organized as 32Mbit x 8 I/Os x 8 banks or 16Mbit x 16 I/Os x 8 bank devices.

JEDEC DDR3 Compliant - 8n Prefetch Architecture - Differential Clock(CK/) and Data Strobe(DQS/) - Double-data rate on DQs, DQS and DM.
Signal Integrity - Configurable DS for system compatibility - Configurable On-Die Termination - ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (240 ohm ± 1%).
Data Integrity - Auto Self Refresh (ASR) by DRAM built-in TS - Auto Refresh and Self Refresh Modes.
Signal Synchronization - Write Leveling via MR settings - R.

Nanya

Part number	NT5CB128M16FP
Manufacturer	Nanya
File Size	3.26 MB
Description	Industrial and Automotive DDR3(L) 2Gb SDRAM
Datasheet	NT5CB128M16FP Datasheet
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DDR3(L) 2Gb SDRAM NT5CB(C)256M8FN / NT5CB(C)128M16FP Nanya Technology Corp.

Published: Sep 4, 2014 |