NT5CB128M16IP - Industrial and Automotive DDR3(L) 2Gb SDRAM

This page provides the datasheet information for the NT5CB128M16IP, a member of the NT5CB256M8IN Industrial and Automotive DDR3(L) 2Gb SDRAM family.

Product Overview

Nanya

Part number	NT5CB128M16IP
Manufacturer	Nanya
File Size	3.45 MB
Description	Industrial and Automotive DDR3(L) 2Gb SDRAM
Datasheet	NT5CB128M16IP Datasheet
Additional preview pages of the NT5CB128M16IP datasheet.

JEDEC DDR3 Compliant - 8n Prefetch Architecture - Differential Clock(CK/) and Data Strobe(DQS/) - Double-data rate on DQs, DQS and DM.
Data Integrity - Auto Self Refresh (ASR) by DRAM built-in TS - Auto Refresh and Self Refresh Modes.
Power Saving Mode - Partial Array Self Refresh (PASR) 1 - Power Down Mode.
Signal Integrity - Configurable DS for system compatibility - Configurable On-Die Termination - ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (.

Other Datasheets by Nanya

Published: Oct 12, 2018 |