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NT5CB128M16JR - Commercial and Industrial DDR3(L) 2Gb SDRAM

Download the NT5CB128M16JR datasheet PDF. This datasheet also covers the NT5CB256M8JQ variant, as both devices belong to the same commercial and industrial ddr3(l) 2gb sdram family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • JEDEC DDR3 Compliant - 8n Prefetch Architecture - Differential Clock(CK/) and Data Strobe(DQS/) - Double-data rate on DQs, DQS and DM.
  • Data Integrity - Auto Self Refresh (ASR) by DRAM built-in TS - Auto Refresh and Self Refresh Modes.
  • Power Saving Mode - Power Down Mode.
  • Signal Integrity - Configurable DS for system compatibility - Configurable On-Die Termination - ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (240 ohm ± 1%).
  • Signal Synchroniza.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (NT5CB256M8JQ-Nanya.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number NT5CB128M16JR
Manufacturer Nanya
File Size 3.54 MB
Description Commercial and Industrial DDR3(L) 2Gb SDRAM
Datasheet download datasheet NT5CB128M16JR Datasheet

Full PDF Text Transcription for NT5CB128M16JR (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for NT5CB128M16JR. For precise diagrams, and layout, please refer to the original PDF.

NTC Proprietary Level: Property DDR3(L)-2Gb J-Die NT5CB(C)256M8JQ/NT5CB(C)128M16JR Commercial and Industrial DDR3(L) 2Gb SDRAM Features  JEDEC DDR3 Compliant - 8n Prefet...

View more extracted text
dustrial DDR3(L) 2Gb SDRAM Features  JEDEC DDR3 Compliant - 8n Prefetch Architecture - Differential Clock(CK/) and Data Strobe(DQS/) - Double-data rate on DQs, DQS and DM  Data Integrity - Auto Self Refresh (ASR) by DRAM built-in TS - Auto Refresh and Self Refresh Modes  Power Saving Mode - Power Down Mode  Signal Integrity - Configurable DS for system compatibility - Configurable On-Die Termination - ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (240 ohm ± 1%)  Signal Synchronization - Write Leveling via MR settings 5 - Read Leveling via MPR  Interface and Power Supply - SSTL_15 for DDR3:VDD/

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