* 0 5 10 15 20 25 VGS VDS GATE
* TO
* SOURCE OR DRAIN
* TO
* SOURCE VOLTAGE (VOLTS) Figure 1a. Capacitance Variation 1000 VGS = 0 V TJ = 25°C 100 10 Ciss Coss Crss 1 10 100 10 VDS, DRAIN
* TO
* SOURCE VOLTAGE (VOLTS) Figure 1b. High Voltage Capacitance Variat
MTP2N40E Datasheet (204.50 KB)
MTP2N40E
204.50 KB
Power field effect transistor.
MTP2N40E Designer’s™ Data Sheet TMOS E FET.™ Power Field Effect Transistor N Channel Enhancement Mode Silicon Gate This high .
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