* ss 300 200 Coss 100 Crss 0 10 5 0 5 10 15 20 25 VGS VDS GATE
* TO
* SOURCE OR DRAIN
* TO
* SOURCE VOLTAGE (VOLTS) Figure 7a. Capacitance Variation 1000 Ciss 100 Coss 10 1 TJ = 25°C VGS = 0 0.1 10 Crss 100 10 VDS, DRAIN
* TO
* SOURCE VOLTAGE (VOLTS) Fig
MTP2N60E Datasheet (206.15 KB)
MTP2N60E
206.15 KB
Power field effect transistor.
MTP2N60E Designer’s™ Data Sheet TMOS E FET.™ Power Field Effect Transistor N Channel Enhancement Mode Silicon Gate This high .
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