* Input Data Rate > 10.7 Gb/s Typical
* Data Dependent Jitter < 15 ps
* Maximum Input Clock Frequency > 7 GHz Typical
* Random Clock Jitter < 0.8 ps RMS
* Low Skew 1:2 LVPECL Outputs, < 15 ps max
* 4:1 Multi
* Level Mux Inputs, Accepts LVPECL, CM
NB7L572
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2.5 v / 3.3 v differential 4:1 mux input to 1:2 lvpecl clock/data fanout/translator.
NB7L572
2.5V / 3.3V Differential 4:1 Mux Input to 1:2 LVPECL Clock/Data Fanout / Translator
Multi
*Level Inputs w/ Internal Termination
The NB.
📁 Related Datasheet
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Multi−Level Inputs w/ Internal Termination
Descript.
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Multi−Level Inputs w/ Internal Termination
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(ON Semiconductor)
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Description
http://onsemi. MARKI.
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(ON Semiconductor)
DATA SHEET .onsemi.
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Multi−Level Inputs with Internal Termination
NB7L14
Des.
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(ON Semiconductor)
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