NB7L572 Datasheet (ON Semiconductor) - 2.5 V / 3.3 V Differential 4:1 Mux Input To 1:2 LVPECL Clock/Data Fanout/Translator

NB7L572, 2.5 V / 3.3 V Differential 4:1 Mux Input To 1:2 LVPECL Clock/Data Fanout/Translator

Pin Name I/O Description 1, 4 5, 8 25, 28 29, 32 IN0, IN0 IN1, IN1 IN2, IN2 IN3, IN3 LVPECL, CML, Non *inverted, Inverted, Differential Clock or Data Inputs.

LVDS Input 2, 6 26, 30 VT0, VT1 VT2, VT3 Internal 100 W Center *tapped Termination Pin for INx / INx 15 18 14, 19 SE

NB7L572 2.5V / 3.3V Differential 4:1 Mux Input to 1:2 LVPECL Clock/Data Fanout / Translator Multi Level Inputs w/ Internal Termination The NB7L572 is a high performance differential 4:1 Clock/Data input multiplexer and a 1:2 LVPECL Clock/Data fanout buffer.

The INx/INx inputs includes internal 50 W termination resistors and will accept differential LVPECL, CML, or LVDS logic levels.

The NB7L572 incorporates a pair of Select pins that will choose one of four differential inputs and will

NB7L572 Features

* Input Data Rate > 10.7 Gb/s Typical

* Data Dependent Jitter < 15 ps

* Maximum Input Clock Frequency > 7 GHz Typical

* Random Clock Jitter < 0.8 ps RMS

* Low Skew 1:2 LVPECL Outputs, < 15 ps max

* 4:1 Multi

* Level Mux Inputs, Accepts LVPECL, CM