* Q0 Q1 0 Q1 Q2 IN1 VT1 IN1 Q2 Q3 50 W 50 W 1 Q3 Q4 VREFAC1 VCC GND Q4 Q5 Q5 Figure 1. Simplified Block Diagram ORDERING INFORMATION See detailed ordering and shipping information on page 8 of this data sheet. © Semiconductor Components Industries, LLC, 2009 1 October, 2009
* Rev. 0
NB7L585R Datasheet (186.54 KB)
NB7L585R
186.54 KB
Differential 1:6 rsecl clock/data distribution.
NB7L585R 2.5V/3.3V, 7GHz/10Gbps Differential 2:1 Mux Input to 1:6 RSECL Clock/Data Fanout Buffer / Translator
Multi
*Level Inputs w/ Internal T.
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Multi−Level Inputs with Internal Termination
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