Description
Pin NO.
16 17
20 21
23
24
BST LX PGND IN EN EP
Descriptions
Mode selection input.Input bias on this pin sets Forced PWM or Forced PWM with pre
biased startup
3.3 V LDO Output.Supply input for the internal analog core.Connect a low
ESR, ceramic capacitor with a minimum value of 2.2 mF from VDD to GND.
Features
- include cycle.
- by.
- cycle current limit, 92% max duty cycle, short.
- circuit protection, and thermal shutdown. Features.
- Wide Input Voltage Range from 2.9 V to 6.0 V.
- Nine Preset Output Voltages (0.6 V, 0.7 V, 0.8 V, 1.0 V, 1.2 V, 1.5 V,
1.8 V, 2.0 V, and 2.5 V).
- Adjustable Output Voltage Down to 0.6 V.
- Adjustable 500 kHz to 2 MHz Switching Frequency.
- Externally Adjustable Soft.
- Start and Able to Start Up with
Pre.
- Bia.
NCP1594A-ONSemiconductor.pdf