MN38663S Datasheet (Panasonic Semiconductor) - NTSC-Compatible CCD Video Signal Delay Element

MN38663S, NTSC-Compatible CCD Video Signal Delay Element

Pin No.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol XIC VSS3 VDD3 VINC1 N.C.

VINVC VGC1 VO1C VDD1 VSS1 VO2Y VGC2 VINC2 SW VINVY VDD2 VSS2 *VBB PCOUT&VCOIN XIV Pin Name 9.545454 MHz clock input GND (3) Power supply (3) Camera signal input (1) No connection Video signal input (C

CCD Delay Line Series MN38663S NTSC-Compatible CCD Video Signal Delay Element Overview The MN38663S is a CCD signal delay element for video signal processing applications.

It contains such components as a threefold-frequency circuit, a shift register clock driver, charge I/O blocks, two CCD analog shift registers switchable between 680.5 and 605 stages, a clamp bias circuit, resampling output amplifiers, and booster circuits.

When the switch input is "L" level, the MN38663S samples the input us

MN38663S Features

* Single 4.4 V power supply Choice of camera and VCR modes, so that both the camera and VCR portions of a video camera with 510 horizontal pixels can use the same MN38663S for signal processing Applications Video cameras 1 MN38663S Block Diagram CCD Delay Line Series VGC1 16 V DD2 17 V SS2 10