MN3867S Datasheet (Panasonic Semiconductor) - PAL-Compatible CCD Video Signal Delay Element

MN3867S, PAL-Compatible CCD Video Signal Delay Element

Pin No.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Notes 1: Always connect VDD1, VDD2, and VDD3 to the same voltage.

2: Always connect VSS1, VSS2, and VSS3 to ground.

MN3867S Symbol XIC VSS3 VDD3 VINC1 N.C.

VINVC VGC1 VO1C VDD1 VSS1 VO2Y VGC2 VINC2 SW VINVY VDD2 VSS2 *VBB PCOUT&VC

CCD Delay Line Series MN3867S PAL-Compatible CCD Video Signal Delay Element Overview The MN3867S is a CCD signal delay element for video signal processing applications.

It contains such components as a threefold-frequency circuit, a shift register clock driver, charge I/O blocks, two CCD analog shift registers switchable between 1700 and 617 stages and between 848.5 and 617 stages, a clamp bias circuit, resampling output amplifiers, and booster circuits.

When the switch input is "L" level, the

MN3867S Features

* Single 5.0 V power supply Choice of camera and VCR modes, so that both the camera and VCR portions of a video camera with 510 horizontal pixels can use the same MN38667S for signal processing Applications Video cameras 1 MN3867S Block Diagram CCD Delay Line Series VGC1 16 V DD2 17 V SS2 10