MN3880S Datasheet (Panasonic Semiconductor) - NTSC CCD Video Signal Delay Element

MN3880S, NTSC CCD Video Signal Delay Element

Pin No.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol VBIASC VOC N.C.

VDD *VBB N.C.

VOY VBIASY VINY N.C.

N.C.

VSS XI N.C.

N.C.

VINC Pin Name Output gate connection (C) Signal output (C) No connection Power supply Substrate connection No connection Signal output (Y) Output gate connection (Y

CCD Delay Line Series MN3880S NTSC CCD Video Signal Delay Element Overview The MN3880S is a CCD signal delay element for video signal processing applications.

It contains such components as a shift register clock driver, charge I/O blocks, two CCD delay elements, a clamp bias circuit, resampling output amplifiers, and booster circuits.

The MN3880S samples the input using the supplied clock signal with a frequency of 7.15909 MHz, twice the NTSC color signal subcarrier frequency, and after adding

MN3880S Features

* Single 4.9 V power supply Single chip combining luminance signal delay element and delay element for chrominance signal after passing through a low pass filter VOY VBIASY (TOP VIEW) SOP016-P-0225 Applications VCRs 1 MN3880S Block Diagram CCD Delay Line Series 12 4 Bias circuit VINC 16 Charg