MN3890S Datasheet - Panasonic Semiconductor

MN3890S NTSC-Compatible CCD 1 H Video Signal Delay Element

Pin No. 1 2 3 4 5 6 7 8 Symbol VIN VBB VDD VSS XI PCOUT & VCOIN VGC VO Function Description Signal input pin Substrate connection pin Power supply Ground 7.16 MHz clock input pin Phase comparator output and voltage controlled oscillator input Output gate connection pin Signal output pin MN3890S R.

CCD Delay Line Series MN3890S NTSC-Compatible CCD 1 H Video Signal Delay Element Overview The MN3890S is a 1 H image delay element of a 4 fSC CMOS CCD and suitable for video signal processing applications. It contains such components as a frequency-doubler circuit, a shift register clock driver, a 906-stage CCD analog shift register, and a resampling output amplifier. The MN3885S drives and samples the 906-stage analog shift register using a redoubled version of the supplied clock signal with a.

MN3890S Features

* Single 5.0 V power supply Energy-saving design based on CMOS process Low EMI levels from clock during driving Applications VCRs, Video cameras Structure and Operation The MN3890S consists of the operational blocks shown in the block diagram. Frequency-doubler circuit When the 7.16 MHz of the doubl

MN3890S Datasheet (53.10 KB)