74HCT73 Datasheet - Philips

Dual JK flip-flop

74HCT73 Features

* s Low-power dissipation s Complies with JEDEC standard no. 7A s ESD protection: x HBM EIA/JESD22-A114-B exceeds 2000 V x MM EIA/JESD22-A115-A exceeds 200 V. s Multiple package options s Speciﬁed from

* 40 °C to +80 °C and from

* 40 °C to +125 °C. Philips Semiconductors 74HC73 Dual JK

74HCT73 General Description

The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC73 is speciﬁed in compliance with JEDEC standard no. 7A. The 74HC is a dual negative-edge triggered JK ﬂip-ﬂop featuring individual J, K, clock (nCP) and reset (nR) inputs; also compleme.

74HCT73 Datasheet (110.18 KB)

74HCT73 Datasheet Preview — Preview of 74HCT73 PDF

Datasheet Details

Part number:

74HCT73

Manufacturer:

Philips

File Size:

110.18 KB

Description:

Dual jk flip-flop.

📁 Related Datasheet

74HCT7030 9-bit x 64-word FIFO register (Philips)

74HCT7046A Phase-locked-loop (NXP)

74HCT7046A Phase-locked-loop (Philips)

74HCT7080 16-bit even/odd parity generator/checker (Philips)

74HCT7245 Octal bus Schmitt-trigger transceiver (Philips)

74HCT7273 Octal D-type flip-flop (Philips)

74HCT74 Dual D-type flip-flop (nexperia)

74HCT74 Dual D-Type Positive-Edge-Triggered Flip-Flips (Texas Instruments)

74HCT74 Dual D-Type Flip-Flop (STMicroelectronics)

74HCT74-Q100 Dual D-type flip-flop (nexperia)

TAGS

74HCT73 Dual flip-flop Philips

Image Gallery

74HCT73 Features

74HCT73 General Description

Datasheet Details

File Size:

Description:

74HCT73 Distributor