Description
The memory array is designed with 512-Mbit Double-DataRate-Two (DDR2) Synchronous DRAMs.
Features
- Auto Refresh (CBR) and Self Refresh Programmable self refresh rate via EMRS2 setting Programmable partial array refresh via EMRS2 settings DCC enabling via EMRS2 setting All inputs and outputs SSTL_1.8 compatible Off-Chip Driver Impedance Adjustment (OCD) and On-Die Termination (ODT) Serial Presence Detect with E2PROM UDIMM Dimensions (nominal): 30 mm high and 133.35 mm wide Based on standard refe.
HYS64T128920_Qimonda.pdf