Description
capacitive loading to the system bus, but adds one cycle to the SDRAM timing.
Features
- Programmable CAS Latencies (3, 4 and 5), Burst Length (4 & 8) and Burst Type.
- Auto Refresh (CBR) and Self Refresh.
- Average Refresh Period 7.8 µs at a TCASE lower than 85°C, 3.9 µs between 85 °C and 95 °C.
- Programmable self refresh rate via EMRS2 setting.
- All inputs and outputs SSTL_18 compatible.
- Off-Chip Driver Impedance Adjustment (OCD) and On-Die Termination (ODT).
- Serial Presence Detect with E2PROM.
- Based on standard re.
HYS72T64301HP-3S-A_Qimonda.pdf