QL3040 Datasheet (QuickLogic Corporation) - PLD Gate pASIC 3 FPGA Combining High Performance and High Density

QL3040, PLD Gate pASIC 3 FPGA Combining High Performance and High Density

QL3040 pASIC 3 FPGA Data Sheet 40,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Device Highlights High Performance & High Density 40,000 Usable PLD Gates with 252 I/Os 300 MHz 16-bit www.DataSheet4U.com Eight Low-Skew Distributed Networks Two array clock/control networks available Counters, 400 MHz Datapaths 0.35 µm four-layer metal non-volatile CMOS process for smalle

QL3040 Features

* 0800 1.0600 1.0400 Kv 1.0200 1.0000 0.9800 www.DataSheet4U.com 0.9600 0.9400 0.9200 3 3.1 3.2 3.3 3.4 3.5 3.6 Supply Voltage (V) Figure 3: Voltage Factor vs. Supply Voltage Temperature Factor vs. Operating Temperature 1.15 1.10 1.05 1.00 0.95 0.90 0.85 -60 -40 -20 0 20 40 60 80 Kt Junction