QL3006 Datasheet (QuickLogic Corporation) - PLD Gate pASIC 3 FPGA Combining High Performance and High Density

QL3006, PLD Gate pASIC 3 FPGA Combining High Performance and High Density

4/ S$6,& )3 $ 'DWD 6KHHW 8VDEOH 3/' DWH S$6,& )3 $ &RPELQLQJ +LJK 3HUIRUPDQFH DQG +LJK 'HQVLW 'HYLFH +LJKOLJKWV +LJK 3HUIRUPDQFH www.DataSheet4U.com 300 MHz 16-bit +LJK 'HQVLW )RXU /RZ6NHZ 'LVWULEXWHG 1HWZRUNV Two array clock/control networks available 6,000 Usable PLD Gates with 82 I/Os Counters, 400 MHz Datapaths 0.35 µm four-layer metal non-volatile CMOS process for smallest die sizes (DVWR8VH )DVW 'HYHORSPHQW &FOHV 100% routable with 100