2305 Datasheet (Renesas) - 3.3V Zero-Delay Clock Buffer

2305, 3.3V Zero-Delay Clock Buffer

The 2305 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications.

The zero-delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10MHz to 133MHz.

The 2305 is an 8-pin version of

2305 Features

* ▪ Phase-Lock Loop clock distribution ▪ 10MHz to 133MHz operating frequency ▪ Distributes one clock input to one bank of five outputs ▪ Zero input-output delay ▪ Output skew < 250ps ▪ Low jitter < 200ps cycle-to-cycle ▪ 2305-1 for Standard drive ▪ 2305-1H for High drive ▪ No external RC network requi