2308B Datasheet (Renesas) - 3.3V ZERO DELAY CLOCK BUFFER

2308B, 3.3V ZERO DELAY CLOCK BUFFER

The 2308B is a high-speed phase-lock loop (PLL) clock multiplier.

It is designed to address high-speed clock distribution and multiplication applications.

The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz.

The

2308B Features

* Phase-Lock Loop Clock Distribution for Applications ranging from 10MHz to 133MHz operating frequency

* Distributes one clock input to two banks of four outputs

* Separate output enable for each output bank

* External feedback (FBK) pin is used to synchronize the out