Datasheet4U Logo Datasheet4U.com

HD74ALVCH162721 - 3.3-V 20-bit Flip Flops

Datasheet Summary

Description

The HD74ALVCH162721’s twenty flip flops are edge triggered D-type flip flops with qualified clock storage.

On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs, provided that the clock enable (CLKEN) input is low.

If CLKEN is high, no data is stored.

📥 Download Datasheet

Datasheet preview – HD74ALVCH162721

Datasheet Details

Part number HD74ALVCH162721
Manufacturer Renesas
File Size 241.55 KB
Description 3.3-V 20-bit Flip Flops
Datasheet download datasheet HD74ALVCH162721 Datasheet
Additional preview pages of the HD74ALVCH162721 datasheet.

📁 Similar Datasheet

  • HD74ALVCH162721 - 3.3-V 20-bit Flip Flops with 3-state Outputs (Hitachi Semiconductor)
  • HD74ALVCH16270 - 12-bit to 24-bit Registered Bus Exchanger with 3-state Outputs (Hitachi Semiconductor)
  • HD74ALVCH162244 - 16-bit Buffers / Drivers with 3-state Outputs (Hitachi Semiconductor)
  • HD74ALVCH162260 - 12-bit to 24-bit Multiplexed D-type Latches with 3-state Outputs (Hitachi Semiconductor)
  • HD74ALVCH162270 - 12-bit to 24-bit Registered Bus Exchanger with 3-state Outputs (Hitachi Semiconductor)
  • HD74ALVCH162334 - 16-bit Universal Bus Driver with 3-state Outputs (Hitachi Semiconductor)
  • HD74ALVCH162373 - 16-bit Transparent D-type Latches with 3-state Outputs (Hitachi Semiconductor)
  • HD74ALVCH162374 - 16-bit Edge triggered D-type Flip Flops with 3-state Outputs (Hitachi Semiconductor)
  • HD74ALVCH16244 - 16-bit Buffers / Drivers with 3-state Outputs (Hitachi Semiconductor)
  • HD74ALVCH16245 - 16-bit Bus Transceivers with 3-state Outputs (Hitachi Semiconductor)
Other Datasheets by Renesas

Full PDF Text Transcription

Click to expand full text
HD74ALVCH162721 3.3-V 20-bit Flip Flops with 3-state Outputs REJ03D0044-0400Z (Previous ADE-205-184B (Z) ) Rev.4.00 Oct.02.2003 Description The HD74ALVCH162721’s twenty flip flops are edge triggered D-type flip flops with qualified clock storage. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs, provided that the clock enable (CLKEN) input is low. If CLKEN is high, no data is stored. A buffered output enable (OE) input can be used to place the twenty outputs in either a normal logic state (high or low level) or a high impedance state. In the high impedance state, the outputs neither load nor drive the bus lines significantly.
Published: |