* gated clock inputs and an overriding clear input. The parallel-in or serial-in modes are established by the shift / load input. When high, this input enables the serial data input and couples the eight flip-flops for serial shifting with each clock pulse. When low, the parallel (broadside) data in
HD74LS166A Datasheet (212.04 KB)
HD74LS166A
212.04 KB
8-bit shift register.
HD74LS166A
8-bit Shift Register
REJ03D0450-0400 Rev.4.00
May 10, 2006
The inputs are buffered to lower the drive requirements to one series 74 or 7.
📁 Related Datasheet
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19.20 20.00 Max 16 9 7.40 Max 6.30
Unit: mm
1 1.3
1.11 Max
8
0.51 Min
2.54 Min 5.06 Max
7.62
2.54 ± 0.25
0.48 ± 0.10
0.25 – 0.05 0° – 15°
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HD74LS166AP - 8-bit Shift Register
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REJ03D0450-0400 Rev.4.00
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The inputs are buffered to lower the drive requirements to one series 74 or 7.
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19.20 20.00 Max 16 9 7.40 Max 6.30
Unit: mm
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0.51 Min
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0.48 ± 0.10
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19.20 20.00 Max 16 9 7.40 Max 6.30
Unit: mm
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0.51 Min
2.54 Min 5.06 Max
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