HD74LS166A - 8-bit Shift Register

Renesas

Datasheet Details

gated clock inputs and an overriding clear input. The parallel-in or serial-in modes are established by the shift / load input. When high, this input enables the serial data input and couples the eight flip-flops for serial shifting with each clock pulse. When low, the parallel (broadside) data inputs are enabled and synchronous loading occurs on the next clock pulse, during parallel loading, serial data flow is inhibited. This, of course, allows the system clock to be free running and the re.

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Renesas HD74LS166A-like datasheet

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