IDT23S09E Datasheet - Renesas

IDT23S09E 3.3V ZERO DELAY CLOCK BUFFER

The IDT23S09E is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 200MHz. The IDT23S09E is a 16-pin ve.

IDT23S09E Features

* Phase-Lock Loop Clock Distribution

* 10MHz to 200MHz operating frequency

* Distributes one clock input to one bank of five and one bank of four outputs

* Separate output enable for each output bank

* Output Skew < 250ps

* Low jitter

IDT23S09E-Renesas.pdf