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ISL80113 Datasheet - Renesas

ISL80113 Low Input Voltage NMOS LDOs

VOUT Output voltage pin. Range 0.5V to 3.3V ADJ VBIAS ADJ pin for externally setting VOUT. Bias voltage pin for internal control circuits. Range 2.9V to 5.5V GND Ground pin PG VOUT in regulation signal. Logic low defines when VOUT is not in regulation. Range 0V to BIAS ENABLE VIN independe.

DATASHEET ISL80111, ISL80112, ISL80113 Ultra Low Dropout 1A, 2A, 3A Low Input Voltage NMOS LDOs FN7841 Rev.4.01 Jun 12, 2020 The ISL80111, ISL80112, and ISL80113 are ultra low dropout LDOs providing the optimum balance between performance, size and power consumption in size constrained designs for data communication, computing, storage and medical applications. These LDOs are specified for 1A, 2A, and 3A of output current and are optimized for low voltage conversions. Operating with a VIN of .

ISL80113 Features

* Ultra low dropout: 75mV at 3A, (typical)

* Excellent VIN PSRR: 70dB at 1kHz (typical)

* ±1.6% assured VOUT accuracy for -40ºC < TJ < +125ºC

* Very fast load transient response

* Extensive protection and reporting features

* VIN range: 0.7V to 3.6V, V

ISL80113 Datasheet (1.07 MB)