* Low power consumption technology
* VDD = single power supply voltage of 2.4 to 5.5 V
* HALT mode
* STOP mode RL78 CPU core
* CISC architecture with 3-stage pipeline
* Minimum instruction execution time: Can be changed from high speed (0.0625 μs: @ 16 MHz operation with high-spee
R5F12067MSP Datasheet (2.85 MB)
R5F12067MSP
2.85 MB
Mcu.
DATASHEET RL78/G15 RENESAS MCU R01DS0420EJ0130 Rev.1.30 Aug 9, 2024 True low-power platform, 54-µA/MHz operating current, TA = 125°C operation, fro.
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