SSTE32882HLB - 1.35V/1.5V REGISTERING CLOCK DRIVER

Renesas

The SSTE32882HLB by Renesas is a 1.35V/1.5V REGISTERING CLOCK DRIVER. Below is the official datasheet preview.

Datasheet Details

Part number	SSTE32882HLB
Manufacturer	Renesas
File Size	1.49 MB
Description	1.35V/1.5V REGISTERING CLOCK DRIVER
Datasheet	SSTE32882HLB-Renesas.pdf
Additional preview pages of the SSTE32882HLB datasheet.

This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock driver with parity is designed for 1.35V and 1.5V VDD operation.

Pinout optimizes DDR3 RDIMM PCB layout.
1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs support stacked DDR3 RDIMMs.
Phase Lock Loop clock driver for buffering one differential clock pair (CK and CK) and distributing to four differential outputs.
Supports LVCMOS switching levels on the RESET and MIRROR inputs.
Checks priority on DIMM-independent data inputs.
Supports dynamic 1T/3T timing transaction and output inversion feature for imp.

📁 SSTE32882HLB Similar Datasheet

Other Datasheets by Renesas

Published: Jan 19, 2020 |