SSTE32882HLB

1.35V/1.5V REGISTERING CLOCK DRIVER

Renesas

SSTE32882HLB Features

* Pinout optimizes DDR3 RDIMM PCB layout

* 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs support stacked DDR3 RDIMMs

* Phase Lock Loop clock driver for buffering one differential clock pair (CK and CK) and distributing to four differential outputs

* Supports L

SSTE32882HLB General Description

This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock driver with parity is designed for 1.35V and 1.5V VDD operation. All inputs are 1.35V and 1.5V CMOS compatible, except the reset (RESET) and MIRROR inputs which are LVCMOS. All outputs are 1.35V and 1.5V CMOS edge-controlled drivers opt.

SSTE32882HLB Datasheet (1.49 MB)