STLC5432 Datasheet - ST Microelectronics

STLC5432 2Mbit CEPT & PRIMARY RATE CONTROLLER DEVICE

STLC5432, CMOS device, interfaces the multiplex system to the physical CEPT Transmission link at 2048Kb/s. Furthermore, thanks to its flexibility, it is the optimum solution also for the ISDN application as PRIMARY RATE CONTROLLER. The receive circuit performances exceed CCITT recommendation and the.

STLC5432 2Mbit CEPT & PRIMARY RATE CONTROLLER DEVICE PRELIMINARY DATA ONE CHIP SOLUTION FROM PCM BUS TO TRANSFORMER (CEPT STANDARD) ISDN PRIMARY ACCESS CONTROLLER (COMPATIBLE WITH ETSI, OPTION 1 AND 2) HDB3/BIN ENCODER AND DECODER ON CHIP MULTIFRAME STRUCTURE HANDLING BUILT IN CRC4 EASY LINK TO ST5451/MK50H25/MK5027 LINK CONTROLLERS. DATA RATE: 2048, 4096 AND 8192 Kb/s FOR MULTIPLEXED APPLICATIONS FOUR LOOPBACK MODES FOR TESTING PSEUDO RANDOM SEQUENCE GENERATOR AND ANALYZER FOR ON-LINE, OFFLINE.

STLC5432 Features

* te) All digital inputs All digital inputs 2.2 XTAL1 input XTAL1 input VCC-0.5 IL = 7mA for pins AL0, AL1, INT, DOUT, HCR, LCR. All other digital outputs: IL = 1mA IL = 7mA for pins AL0, AL1, 2.4 INT, DOUT, HCR, LCR. 2.4 All other digital outputs: IL = 1mA Any digita

STLC5432 Datasheet (391.31 KB)