K7D323674A Datasheet - Samsung Electronics

K7D323674A 1Mx36 & 2Mx18 SRAM

The K7D323674A and K7D321874A are 37,748,736 bit Synchronous Pipeline Burst Mode SRAM devices. They are organized as 1,048,576 words by 36 bits for K7D323674A and 2,097,152 words by 18 bits for K7D321874A, fabricated using Samsung's advanced CMOS technology. Single differential HSTL level clock, K a.

K7D323674A K7D321874A Document Title 32M DDR SYNCHRONOUS SRAM Advance www.DataSheet4U.com 1Mx36 & 2Mx18 SRAM Revision History Rev No. Rev. 0.0 Rev. 0.1 History Initial document. Remove /G operation thru the Spec. - Remove /G from PUNCTIONAL BLOCK DIAGRAM, PIN CONFIGURATION, TRUTH TABLE and TIMING WAVEFORMs Add 300MHz Speed bin. - Add Part ID at ORDERING INFORMATION & I DD30 at DC CHARACTERISTICS Change ILI and I Lo at DC CHARCATERISTICS - ILI : MIN -1 -> -3, MAX 1 -> 3, ILo : MIN -1 -> -5, MAX.

K7D323674A Features

* : 1.5V V DDQ -> 1.5~.1.8V V DDQ - In RECOMENDED DC OPERATING CONDITIONS : Max VDDQ : 1.6 -> 1.9 Change TRUTH TABLE : Remove Clock Stop Change DC CHARACTERISTICS - x36 IDD : IDD50 : 950 -> 1050, I DD45 : 850 -> 950, IDD40: 800 -> 860, IDD30 : 750 -> 760 - x18 IDD: IDD50 : 850 -> 1000, I DD45 : 800 ->

K7D323674A_SamsungElectronics.pdf