K7R161884B - 512Kx36 & 1Mx18 QDR II b4 SRAM
Input Clock Input Clock for Output Data Output Echo Clock DLL Disable when low Address Inputs Data Inputs 1 NOTE Q0-35 W R BW0, BW1,BW2, BW3 VREF ZQ VDD VDDQ VSS TMS TDI TCK TDO NC Data Outputs Write Control Pin,active when low Read Control Pin,active when low Block Write Control Pin,active when l
K7R163684B K7R161884B Document Title 512Kx36 & 1Mx18 QDRTM II b4 SRAM 512Kx36-bit,1Mx18-bit QDRTM II b4 SRAM Revision History Rev.
No.
0.0 0.1 History 1.
Initial document.
1.
Change the Boundary scan exit order.
2.
Correct the Overshoot and Undershoot timing diagram.
1.
Change JTAG Block diagram 1.
Add the speed bin (-25) 1.
Correct the JTAG ID register definition 2.
Correct the AC timing parameter (delete the tKHKH Max value) 1.
Change the Maximum Clock cycle time.
2.
Correct the 165FBGA pac
K7R161884B Features
* 1.8V+0.1V/-0.1V Power Supply.
* DLL circuitry for wide output data valid window and future freguency scaling.
* I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/-0.1V for 1.8V I/O.
* Separate independent read and write data ports with concurrent read and w
