Description
K7R163684B K7R161884B Document Title 512Kx36 & 1Mx18 QDRTM II b4 SRAM 512Kx36-bit,1Mx18-bit QDRTM II b4 SRAM Revision History Rev.No.0.0 0.1 Hist.
Input Clock Input Clock for Output Data Output Echo Clock DLL Disable when low Address Inputs Data Inputs 1 NOTE
Q0-35 W R BW0, BW1,BW2, BW3 VREF ZQ.
Features
* 1.8V+0.1V/-0.1V Power Supply.
* DLL circuitry for wide output data valid window and future freguency scaling.
* I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/-0.1V for 1.8V I/O.
* Separate independent read and write data ports with concurrent read and w
