K7R641882M - 2Mx36 & 4Mx18 & 8Mx9 QDRTM II b2 SRAM

Samsung semiconductor

K7R641882M Datasheet Preview — Preview of K7R641882M PDF

Datasheet Details

Part number	K7R641882M
Manufacturer	Samsung semiconductor
File Size	364.61 KB
Description	2Mx36 & 4Mx18 & 8Mx9 QDRTM II b2 SRAM
Datasheet	K7R641882M_Samsungsemiconductor.pdf

K7R641882M Product details

Description

Input Clock Input Clock for Output Data Output Echo Clock DLL Disable when low Address Inputs Data Inputs 1 NOTE Q0-35 W R BW0, BW1,BW2, BW3 VREF ZQ VDD VDDQ VSS TMS TDI TCK TDO NC Data Outputs Write Control Pin,active when low Read Control Pin,active when low Block Write Control Pin,active when low Input Reference Voltage Output Driver Impedance Control Input Power Supply ( 1.8 V ) Output Power Supply ( 1.5V or 1.8V ) Ground JTAG Test Mode Select JTAG Test Data Input JTAG Test Clock JTAG Test

Features

1.8V+0.1V/-0.1V Power Supply.
DLL circuitry for wide output data valid window and future freguency scaling.
I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/-0.1V for 1.8V I/O.
Separate independent read and write data ports with concurrent read and write operation.
HSTL I/O.
Full data coherency, providing most current data.
Synchronous pipeline read with self timed early write.
Registered address, control an.

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Published: Apr 7, 2005 |