Description
Pin Name K, K SAn DQn SW SWa SWb SWc SWd ZZ VDD Pin Description Differential Clocks Synchronous Address Input Bi-directional Data Bus Synchronous Global Write Enable Synchronous Byte a Write Enable Synchronous Byte b Write Enable Synchronous Byte c Write Enable Synchronous Byte d Write Enable Asynchronous Power Down Core Power Supply Pin Name VDDQ M 1, M 2 G SS TCK TMS TDI TDO VSS NC Pin Description Output Power Supply Read Protocol Mode Pins ( M1=VSS, M2=VDD ) Asynchronous Output Enable Synchro
Features
- 128Kx36 or 256Kx18 Organizations. 3.3V Core Power Supply. LVTTL Input and Output Levels. Differential, PECL Clock Inputs K, K. Synchronous Read and Write Operation Registered Input and Registered Output Internal Pipeline Latches to Support Late Write. Byte Write Capability(four byte write selects, one for each 9bits) Synchronous or Asynchronous Output Enable. Power Down Mode vi.