KM718FV4021 Datasheet - Samsung semiconductor

KM718FV4021 (KM736FV4021 / KM718FV4021) 128Kx36 & 256Kx18 Synchronous Pipelined SRAM

Pin Name K, K SAn DQn SW SWa SWb SWc SWd ZZ VDD Pin Description Differential Clocks Synchronous Address Input Bi-directional Data Bus Synchronous Global Write Enable Synchronous Byte a Write Enable Synchronous Byte b Write Enable Synchronous Byte c Write Enable Synchronous Byte d Write Enable Asynch.

KM736FV4021 KM718FV4021 Document Title 128Kx36 & 256Kx18 Synchronous Pipelined SRAM 128Kx36 & 256Kx18 SRAM Revision History Rev. No. Rev. 0.0 Rev. 0.1 History - Preliminary specification release - Change specification format. No change was made in parameters. - Updated IDD, ISB and Input High Level. Updated tKHKL, tKLKH, tKHQX, tKHQX1 and AC Test Conditions. For JTAG, updated Vendor Definition and added tSVCH/tCHSX. - Final specification release Draft Date Remark Preliminary April, 1997 P.

KM718FV4021 Features

* 128Kx36 or 256Kx18 Organizations. 3.3V Core Power Supply. LVTTL Input and Output Levels. Differential, PECL Clock Inputs K, K. Synchronous Read and Write Operation Registered Input

KM718FV4021 Datasheet (350.04 KB)