K7P401822B Datasheet - Samsung

K7P401822B SRAM

Pin Name K, K SAn DQn SS SW SWa SWb SWc SWd M1, M2 Pin Description Differential Clocks Synchronous Address Input Bi-directional Data Bus Synchronous Select Synchronous Global Write Enable Synchronous Byte a Write Enable Synchronous Byte b Write Enable Synchronous Byte c Write Enable Synchronous By.

K7P403622B K7P401822B 128Kx36 & 256Kx18 SRAM Document Title 128Kx36 & 256Kx18 Synchronous Pipelined SRAM Revision History Rev. No. Rev. 0.0 History - Initial Document. Rev. 0.1 - Update Pin Discription. (M2=VDDQ -> M2=VDD) - Add AC characteristics. (250Mhz, 166Mhz) Rev. 0.2 - Update DC CHARACTERISTICS x36 : IDD25 : TBD -> 370, IDD20 -> 340, IDD16 -> 320. x18 : IDD25 : TBD -> 360, IDD20 -> 330, IDD16 -> 310. Rev. 1.0 - Final Version Rev. 1.1 - Add single ended or differential LVTTL c.

K7P401822B Features

* 128Kx36 or 256Kx18 Organizations.

* 3.3V VDD, 2.5/3.3V VDDQ.

* LVTTL Input and Output Levels.

* Differential, PECL clock / Single ended or differential LVTTL clock Inputs

* Synchronous Read and Write Operation.

* Registered Input and Registered Outpu

K7P401822B Datasheet (277.23 KB)