K7P401822B Description
K7P403622B K7P401822B 128Kx36 & 256Kx18 SRAM Document Title 128Kx36 & 256Kx18 Synchronous Pipelined SRAM Revision History Rev.No.Rev.0.0 Histo.
Pin Name K, K SAn DQn SS SW SWa SWb SWc SWd
M1, M2
Pin Description Differential Clocks Synchronous Address Input Bi-directional Data Bus Synchronous.
K7P401822B Features
* 128Kx36 or 256Kx18 Organizations.
* 3.3V VDD, 2.5/3.3V VDDQ.
* LVTTL Input and Output Levels.
* Differential, PECL clock / Single ended or differential LVTTL
clock Inputs
* Synchronous Read and Write Operation.
* Registered Input and Registered Outpu
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