K7P403622M Datasheet (Samsung)

K7P403622M, SRAM

Pin Name K, K SAn DQn SW SWa SWb SWc SWd ZZ VDD Pin Description Differential Clocks Synchronous Address Input Bi-directional Data Bus Synchronous Global Write Enable Synchronous Byte a Write Enable Synchronous Byte b Write Enable Synchronous Byte c Write Enable Synchronous Byte d Write Enable Asyn

K7P403622M K7P401822M 128Kx36 & 256Kx18 SRAM Document Title 128Kx36 & 256Kx18 Synchronous Pipelined SRAM Revision History Rev.

No.

History Rev.

0.0 - Preliminary specification release Rev.

0.1 - Change specification format.

No change was made in parameters.

Rev.

0.2 Rev.

1.0 - Updated IDD, ISB and Input High Level.

Updated tKHKL, tKLKH, tKHQX, tKHQX1 and AC Test Conditions.

For JTAG, updated Vendor Definition and added tSVCH/tCHSX.

- Final specification release Draft Date April, 1997

K7P403622M Features

* 128Kx36 or 256Kx18 Organizations.

* 3.3V Core Power Supply.

* LVTTL Input and Output Levels.

* Differential, PECL Clock Inputs K, K.

* Synchronous Read and Write Operation

* Registered Input and Registered Output

* Internal Pipeline Latches t