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KM48S8030C 2M x 8Bit x 4 Banks Synchronous DRAM

KM48S8030C Description

KM48S8030C Revision History Revision 0.0 (Oct., 1998) * PC133 first published.Preliminary PC133 CMOS SDRAM REV.0 Oct.'98 KM48S8030C 2M x.
The KM48S8030C is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 8 bits, fabricated with SAMSUNG′s high pe.

KM48S8030C Features

* JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency 3 only -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at

KM48S8030C Applications

* ORDERING INFORMATION Part No. KM48S8030CT-G/FA Max Freq. 133MHz (CL 3) Interface Package LVTTL 54 TSOP(II) FUNCTIONAL BLOCK DIAGRAM I/O Control LWE LDQM Data Input Register Bank Select 2M x 8 Sense AMP 2M x 8 2M x 8 2M x 8 Refresh Counter Ou

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Datasheet Details

Part number
KM48S8030C
Manufacturer
Samsung semiconductor
File Size
82.55 KB
Datasheet
KM48S8030C_Samsungsemiconductor.pdf
Description
2M x 8Bit x 4 Banks Synchronous DRAM

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8Bit Banks Synchronous DRAM Samsung semiconductor
Samsung semiconductor KM48S8030C-like datasheet